1. Field of the Invention
This invention relates in general to data communication systems, and in particular to high performance data communication systems having a Transfer Progress Alert (TPA) module in a peripheral interface adapter supporting pipelined operations, to create an alert condition when a pre-specified amount of data has been transferred on the internal system bus.
2. Description of Related Art
Digital communication over a communication channel is well known in the art. Modern data communication systems often have multiple high performance data processors and generally include a plurality of peripheral interfaces connected to the data processors by one or more internal buses. High performance bus architectures, such as the PCI bus architecture, provide a hardware mechanism for transferring large sequential groups of data between a peripheral interface and a processor""s memory, via burst cycles.
Applications which move large data blocks from an external interface to memory space and from memory space to storage media often break this transfer into smaller, individual blocks to achieve more overlapping of event processing in an effort to improve system response time. The pipelined operations on smaller data blocks are specifically desired in systems where data are buffered prior to transfer elsewhere in the system, or where an intermediate data reformatting or data compression on the data in a memory is required, prior to its transfer to the storage medium, which may be a magnetic device such as tape or disk. Thus processing the data in individual blocks enables pipelined operations, allowing such operations as transfer of incoming blocks, post-processing steps, and transfer to storage media to occur on different data blocks simultaneously. This creates a much more efficient data transfer process than storing the entire large data block in the memory, followed by the entire block post-processing, and subsequent sending the entire data block to the storage medium.
However, processing smaller, individual blocks of data, although providing overall efficiency advantages, presents a problem for the post-processing operation control software to determine when exactly a given block is ready for its post-processing step. Therefore, there is a need in a peripheral interface adapter for a Transfer Progress Alert (TPA) module, which can create an alert signal when a pre-specified amount of data has been transferred on the internal system bus, to insure timely start of a pipelined operation on the transferred individual block of data for effective processing.
The foregoing and other objects, features, and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments which makes reference to several drawing figures.
One preferred embodiment of the present invention is a data communication system for fast processing of a data transfer load, divided in individual data blocks. The processing is optimizing the overlap of pipelined operations, including data transfers and post-processing performed on individual data blocks. The system includes at least one peripheral interface adapter having an internal bus connected to a peripheral interface, a DMA channel connected to the internal bus facilitating the DMA transfer of individual data blocks, and a Transfer Progress Alert (TPA) module connected to the internal bus. The system further includes a bridge placed between the internal bus and at least one external bus. Each external bus is connected to a data storage device, a main memory, and a main processor. The bridge is connecting a processor, a post-processing module and a memory.
The internal bus is transferring individual data blocks between the peripheral interface and the memory. The TPA module is determining when each of the transferred individual data blocks has been transferred on the internal bus and is ready for a post-processing operation in the post-processing module. The pipelined operations occur on different individual data blocks simultaneously, and include transferring incoming individual data blocks, at least one post-processing operation, and transferring the processed data, until all individual data blocks from the data transfer load are processed. The TPA module further generates an interrupt alerting a TPA control software, executed in the processor. The control software initializes the TPA module and the DMA channel with the pre-defined individual data block size, starting address and direction control.
The individual data blocks having customer-defined data are assigned to the internal bus addresses in a pre-determined address region, and the TPA module and control software monitor transfers in that particular address region and ignore transfers in other address regions. The TPA module may also include an error detection module for performing an error detection operation on the customer-defined data transferred on the internal bus, for ascertaining the integrity of the transferred data. The post-processing operation may include buffering, data reformatting, data compression or decompression.
Another preferred embodiment of the present invention is a peripheral interface adapter in a data communication system for fast processing of a data transfer load, divided in individual data blocks. The processing is optimizing the overlap of pipelined operations, including data transfers and post-processing performed on individual data blocks. The adapter is connected to a bridge attached to an external bus connected to a data storage device, a main memory, and a main processor. The bridge connects a processor, a post-processing module and a memory. The adapter includes an internal bus connected to a peripheral interface and a DMA channel connected to the internal bus assisting in the DMA transfer of individual data blocks. It also includes a Transfer Progress Alert (TPA) module connected to the internal bus. The internal bus transfers individual data blocks between the peripheral interface and the memory. The TPA module determines when each transferred individual data block is ready for a post-processing operation in the post-processing module. The pipelined operations are occurring on different individual data blocks simultaneously, and include transferring the incoming individual data blocks, at least one post-processing operation, and transferring the processed data, until all individual data blocks from the data transfer load are processed.
Yet another preferred embodiment of the present invention is a method for optimizing processing of a data transfer load, divided in individual data blocks, by simultaneously performing pipelined operations on different individual data blocks, thus optimizing the overlap of pipelined operations. The method is being used in a data communication system and includes the following steps: (a) initializing the TPA module with a pre-defined individual data block size and determining a key for selecting and monitoring transfers with transfer addresses within a pre-determined address region; and (b) continuously repeating following steps until all monitored individual data blocks from the data transfer load are processed: (c) transferring incoming individual data blocks on a bus between a peripheral device and a memory, (d) monitoring in a Transfer Progress Alert (TPA) module, connected to the bus, the individual data blocks having transfer addresses determined to belong in the pre-determined address region; (e) determining in the TPA module when each monitored transferred individual data block is ready for a post-processing operation; (f) generating an interrupt alerting a TPA control software to start the post-processing operation and keeping an interrupt line transferring the interrupt active, until all individual data blocks from the data transfer load are post-processed; (g) performing at least one post-processing operation; and (h) transferring the processed data to a peripheral storage device.
The method further includes a step for performing an error detection operation on the monitored individual data blocks transferred on the bus, for ascertaining the integrity of the transferred data. The error detection operation includes a creation of a resultant checksum obtained by performing an EXCLUSIVE-OR (XOR) operation on the corresponding bits of the newly transferred data and a stored resultant checksum from the previous data transfers.